`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   19:49:11 05/04/2013
// Design Name:   RegisterSet
// Module Name:   T:/Lab3/tb_RegisterSet.v
// Project Name:  Lab3
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: RegisterSet
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module tb_RegisterSet;

	// Inputs
	reg [3:0] data_in;
	reg [1:0] addr_in;
	reg ldr;
	reg sum;
	reg cmp;
	reg mul;
	reg [7:0] alu_data_in;
	reg read;

	// Outputs
	wire [3:0] REGA;
	wire [3:0] REGB;
	wire [3:0] data_out;

	// Instantiate the Unit Under Test (UUT)
	RegisterSet #(.N(4)) uut (
		.data_in(data_in), 
		.addr_in(addr_in), 
		.ldr(ldr), 
		.sum(sum), 
		.cmp(cmp), 
		.mul(mul), 
		.alu_data_in(alu_data_in), 
		.read(read), 
		.REGA(REGA), 
		.REGB(REGB), 
		.data_out(data_out)
	);

	initial begin
		// Initialize Inputs
		data_in = 0;
		addr_in = 0;
		ldr = 0;
		sum = 0;
		cmp = 0;
		mul = 0;
		alu_data_in = 0;
		read = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here
		sum <= 1'b1;
		alu_data_in <= 8'b10100101;
		
		#10;
		sum <= 1'b0;
		
		#90;
		ldr <= 1'b1;
		data_in <= 4'hF;
		addr_in <= 2'b00;
		
		#10;
		ldr <= 1'b0;
		
		#90;
		mul <= 1'b1;
		data_in <= 4'hA;
		addr_in <= 2'b01;
		
		#10;
		mul <= 1'b0;
		
		#90;
		addr_in <= 2'b00;
		read <= 1'b1;
		
		#110;
		addr_in <= 2'b01;

	end
      
endmodule

